After ordering the wrong buffer chip for my Logic Cube I started poking around and managed to get a commercial rom to run. It seems my issues are a result of timing problems with my new memory mapping module. The attempt shown below locked up at the title screen but I have since managed to start the demo video that follows. Unfortunately since I haven’t implemented sprites its less of a video and more of a static background. Assuming the chip that came in today is the correct version I hope to be running on 32 channels and make more progress this weekend.
It’s been a little while since I’ve posted any progress on any of my projects. I’ve been recently employed as a full time design engineer and have finally transitioned back into a schedule that allows me to work on some of my own interests again. I’ve started up working on my NES emulator and had my first success loading a cartridge from an SD Card. I’m stuck again as the emulator locks up when after it’s partially rendered the screen. Debugging has gotten more difficult as time goes on as it now takes 15-20 minutes to compile the design and only having 16 channels on my logic analyzer means recompiling more frequently to figure out what’s gone wrong. I have parts on order to perform an upgrade to 32 channels but until then I expect progress will be a bit slow. I’m hoping to have the parts installed and be able to read the entire address and data buses along with any status bits I need by the end of the week.
I’ve managed to get the nestest rom to run on my emulator. I’m still nowhere near complete but this is a good first step. Video is working, at least without sprites. Control input works, although there’s a bug floating around in there somewhere I’m currently working on getting the APU ( Audio Processing Unit) up and running. Below is a video of my emulator passing all standard opcode tests.
I’ve made significant progress since my first stumbling block. I’ve rewritten my 6502 core so that it is synthesizable and have successfully deployed it to my nanoboard. I have been able to tweak the data bus such that I can communicate with the internal cartridge, my PPU, and the external SRAM available on the nanoboard. This has been pretty tricky since it has been taking over 10 minutes to synthesize and my logic analyzer only has 16 Channels. I’ve found some methods to mitigate these issues and after uncovering a couple of fatal bugs in my PPU Core an image was finally rendered. The rendered screen isn’t what is expected but it is generating tiles from the cartridge data. If you look closely you’ll be able to see some blurry 8’s, 4’s commas and colons.
There’s an amazing project known as Visual 6502. They have created a transistor level net-list of the 6502 processor which can in turn be converted into synthesizable VHDL. As nice as this is, I’ve decided that would be far too easy and am going to go ahead and emulate the 6502 core before I fool around with a proper simulation. I’ve already poured through the available documents and laid out a framework for my emulation. The capture below is the first result from that process. That is the emulator executing the opcode 0x01 (Inderect X indexed OR with the accumulator) The A register isn’t actually visable but the processor is successfully loading the data from my simulated ROM and jumping to the correct memory locations based on the code I’ve provided. There is still a long way to go before the process is complete, but it is well on its way.