I’ve managed to get the nestest rom to run on my emulator. I’m still nowhere near complete but this is a good first step. Video is working, at least without sprites. Control input works, although there’s a bug floating around in there somewhere I’m currently working on getting the APU ( Audio Processing Unit) up and running. Below is a video of my emulator passing all standard opcode tests.
I’ve made significant progress on my 6502 FPGA Emulation, and even have a mostly complete layout of the NES Picture Processing Unit. I set up a test-bench that included RAM and cartridge simulation and logged the processor output to a text file that could be compared to the “golden” nestest log. I was able to debug all of the documented instructions and had begun to implement some of the undocumented instructions when I decided to try and load the processor into my FPGA. Unfortunately, this is where I learned that just because something can be simulated doesn’t mean it can be synthesized.
There’s an amazing project known as Visual 6502. They have created a transistor level net-list of the 6502 processor which can in turn be converted into synthesizable VHDL. As nice as this is, I’ve decided that would be far too easy and am going to go ahead and emulate the 6502 core before I fool around with a proper simulation. I’ve already poured through the available documents and laid out a framework for my emulation. The capture below is the first result from that process. That is the emulator executing the opcode 0x01 (Inderect X indexed OR with the accumulator) The A register isn’t actually visable but the processor is successfully loading the data from my simulated ROM and jumping to the correct memory locations based on the code I’ve provided. There is still a long way to go before the process is complete, but it is well on its way.