NES FPGA: Some Tricks Required

I’ve run into a bit of a road block with my NES Emulation.  I’ve been trying to keep as much of the project as possible in standard VHDL without relying on pre-built libraries or modules.  In order to make testing, as well as end-result use, easier I’d like to be able to load files off of an SD Card using the FAT file system.  Unfortunately attempting to do this in VHDL seems far from straightforward and is certainly more involved than I’m looking to get for this project.  As such I’ve resorted to a wishbone based TSK3000 processor module and some C code to perform FAT related functions, parsing of the INES header, and all cartridge I/O functions.


At this point I’ve been moderately successful with this implementation.  Mounting the FAT file system works.  I can read the available files and load the desired file.  I can even get the nestest rom to run after loading it from the SD Card.  There is a catch though,  and it is pretty big.  In order for the loaded file to run I have to slow the NES’s clock down about 50x.  It’s not going to be possible to get  any meaningful gain out of the processor and I don’t want to rearrange the entire project to make use of the shared memory bus.  I’ve used up both SDRAM Chips (one for the CPU and one for the PPU) so I’m going to have to do some consolidation.


There is more than enough memory available in a single SDRAM chip for the entire project.  The problem is that I need to be able to access each memory location simultaneously (CPU RAM, PPU RAM, Cartridge) and the chips are single port.  I intend on solving this with another VHDL module.  Using the 50MHz clock should allow me to fake a triple port or more memory chip by sequentially reading out the requested memory addresses and latching them to independent outputs.

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