I’ve made significant progress on my 6502 FPGA Emulation, and even have a mostly complete layout of the NES Picture Processing Unit. I set up a test-bench that included RAM and cartridge simulation and logged the processor output to a text file that could be compared to the “golden” nestest log. I was able to debug all of the documented instructions and had begun to implement some of the undocumented instructions when I decided to try and load the processor into my FPGA. Unfortunately, this is where I learned that just because something can be simulated doesn’t mean it can be synthesized.
The synthesizer choked on my design, and it may have given me some feedback if a let it churn for a while I decided to cut my losses and redesign my core. My original code was admittedly inefficient, and generally terrible, so I was expecting to make a second version anyway. I was able to perform numerous simulations and learned a lot along the way, so I’m satisfied with what was accomplished. I’d say I’m about 50% complete on my second attempt and should have much more success in the synthesis department.
