The heart of the VGA controller described in previous articles is a modified binary counter. The VHDL code provided below is a simple 4 bit counter with clock enable and reset inputs. The 4BitCounter_Test file provides a testbench to stimulate the counter and verify it’s operation.
A counter can also be implemented as an altium designer schematic, writing no VHDL, with little effort. In this case an 8 bit counter is used to simplify connection to the on board LEDs. A clock divider is used to create a 2 Hz clock signal to drive the counter. When uploaded to the FPGA board the LEDs will cycle indicating that the counter is working.
Both the VHDL files and designer schematic are available for download at the end of this post.
4BitCounter_VHDL.vhd
[cc lang="vhdl"]library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Counter is
port(
Clock, Enable, Reset: in STD_LOGIC;
Output : out STD_LOGIC_VECTOR(0 to 3)
);
end Counter;
architecture Counter_Behavior of Counter is
signal tempOutput : STD_LOGIC_VECTOR(0 to 3);
begin process(Clock, Reset)
begin
if Reset = '1' then
tempOutput <= "0000";
elsif (Clock'event and Clock = '1') then
if Enable='0' then
if tempOutput = "1111" then
tempOutput <= "0000";
else
tempOutput <= tempOutput +1;
end if;
else
tempOutput <= tempOutput;
end if;
end if;
end process;
Output <= tempOutput;
end Counter_behavior;
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4BitCounter_Test.vhdtst
[cc lang="vhdl"]entity CounterTest is
end;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
architecture TestBench of CounterTest is
component Counter
port(Clock, Enable, Reset : in STD_LOGIC;
Output : out STD_LOGIC_VECTOR(0 to 3)
);
end component;
signal Clock, Enable, Reset: STD_LOGIC;
signal Output : STD_LOGIC_VECTOR(0 to 3);
constant ClockSig : time := 1 NS;
begin
ClockGen : process is
begin
Clock <= '0' after ClockSig, '1' after 2*ClockSig;
wait for 2*ClockSig;
end process ClockGen;
Enable <= '0', '1' after 40 NS, '0' after 50 NS;
Reset <= '1', '0' after 5 NS, '1' after 20NS, '0' after 25 NS;
M: Counter port map (Clock, Enable, Reset, Output);
end TestBench;
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File Downloads:
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