After ordering the wrong buffer chip for my Logic Cube I started poking around and managed to get a commercial rom to run. It seems my issues are a result of timing problems with my new memory mapping module. The attempt shown below locked up at the title screen but I have since managed to start the demo video that follows. Unfortunately since I haven’t implemented sprites its less of a video and more of a static background. Assuming the chip that came in today is the correct version I hope to be running on 32 channels and make more progress this weekend.
It’s been a little while since I’ve posted any progress on any of my projects. I’ve been recently employed as a full time design engineer and have finally transitioned back into a schedule that allows me to work on some of my own interests again. I’ve started up working on my NES emulator and had my first success loading a cartridge from an SD Card. I’m stuck again as the emulator locks up when after it’s partially rendered the screen. Debugging has gotten more difficult as time goes on as it now takes 15-20 minutes to compile the design and only having 16 channels on my logic analyzer means recompiling more frequently to figure out what’s gone wrong. I have parts on order to perform an upgrade to 32 channels but until then I expect progress will be a bit slow. I’m hoping to have the parts installed and be able to read the entire address and data buses along with any status bits I need by the end of the week.
I’ve made significant progress since my first stumbling block. I’ve rewritten my 6502 core so that it is synthesizable and have successfully deployed it to my nanoboard. I have been able to tweak the data bus such that I can communicate with the internal cartridge, my PPU, and the external SRAM available on the nanoboard. This has been pretty tricky since it has been taking over 10 minutes to synthesize and my logic analyzer only has 16 Channels. I’ve found some methods to mitigate these issues and after uncovering a couple of fatal bugs in my PPU Core an image was finally rendered. The rendered screen isn’t what is expected but it is generating tiles from the cartridge data. If you look closely you’ll be able to see some blurry 8’s, 4’s commas and colons.
A video engineer, or really anybody who cares, would tell you that I’ve created a pretty inaccurate representation of the SMPTE color bar test pattern. As I’m not actually trying to calibrate any monitors I don’t fall into this category. I’ve modeled my test screen off of the Wikipedia description of SMPTE color bars. This project only generates a color simulation, ignoring the I and Q vectors, pluge pulse, and other underlying embedded signals. I’m satisfied with the results of this project and consider the original goal to be accomplished. Modifications to the code will most likely be required when it is integrated into the final NES project, but that is much farther down the road. The updated color generator code as well as a download link to the entire project are provided below.
Continue reading “FPGA NES: VGA (Part 3)”
The heart of the VGA controller described in previous articles is a modified binary counter. The VHDL code provided below is a simple 4 bit counter with clock enable and reset inputs. The 4BitCounter_Test file provides a testbench to stimulate the counter and verify it’s operation.
A counter can also be implemented as an altium designer schematic, writing no VHDL, with little effort. In this case an 8 bit counter is used to simplify connection to the on board LEDs. A clock divider is used to create a 2 Hz clock signal to drive the counter. When uploaded to the FPGA board the LEDs will cycle indicating that the counter is working.
Both the VHDL files and designer schematic are available for download at the end of this post.