Apr 17

NES FPGA : Mini Breakthroughs

I’ve made significant progress since my first stumbling block.  I’ve rewritten my 6502 core so that it is synthesizable and have successfully deployed it to my nanoboard.  I have been able to tweak the data bus such that I can communicate with the internal cartridge, my PPU, and the external SRAM available on the nanoboard.  This has been pretty tricky since it has been taking over 10 minutes to synthesize and my logic analyzer only has 16 Channels.  I’ve found some methods to mitigate these issues and after uncovering a couple of fatal bugs in my PPU Core an image was finally rendered.  The rendered screen isn’t what is expected but it is generating tiles from the cartridge data. If you look closely you’ll be able to see some blurry 8′s, 4′s commas and colons.

IMG_20130416_013526

 

Read the rest of this entry »

Apr 05

Of Simulation and Synthesis

I’ve made significant progress on my 6502 FPGA Emulation, and even have a mostly complete layout of the NES Picture Processing Unit.  I set up a test-bench that included RAM and cartridge simulation and logged the processor output to a text file that could be compared to the “golden” nestest log.  I was able to debug all of the documented instructions and had begun to implement some of the undocumented instructions when I decided to try and load the processor into my FPGA. Unfortunately, this is where I learned that just because something can be simulated doesn’t mean it can be synthesized.

Log Comparison

Read the rest of this entry »

Mar 22

FPGA 6502 Emulator: First Life

There’s an amazing project known as Visual 6502.  They have created a transistor level net-list of the 6502 processor which can in turn be converted into synthesizable VHDL.  As nice as this is, I’ve decided that would be far too easy and am going to go ahead and emulate the 6502 core before I fool around with a proper simulation.  I’ve already poured through the available documents and laid out a framework for my emulation.  The capture below is the first result from that process.  That is the emulator executing the opcode 0×01 (Inderect X indexed OR with the accumulator)  The A register isn’t actually visable but the processor is successfully loading the data from my simulated ROM and jumping to the correct memory locations based on the code I’ve provided.  There is still a long way to go before the process is complete, but it is well on its way.

 

First OPCODE

Mar 22

MSGEQ7 Arduino Library

The digital section of my Bright Light Controller is fully functional and I’ve gone ahead and made a library to help interface with the MSGEQ7 IC.  As of Version 0.1 the library will probably only function on a 16MHz or slower Arduino.  This shouldn’t be too difficult to modify, but I haven’t gotten around to it yet.  A video demonstration of the library performing a “readAll” is provided below.

The library is available here: https://github.com/EngineeredEntropy/MSGEQ7

Documentation: https://github.com/EngineeredEntropy/MSGEQ7/wiki/MSGEQ7-Library-Documentation

Mar 20

dllhost.exe High Processor Usage Fix

If you’re having problems with dllhost.exe consuming a lot of resources, along with problems viewing folders in windows explorer it may not be caused by malware.  The quick explanation is that it could be related to a corrupt media file, with a decent probability that file is on your Desktop. The screenshot below shows some of the problems I was having with windows explorer; thumbnails wouldn’t show up and the sidebar wouldn’t populate.

 

ExplorerLag

Read the rest of this entry »

Older posts «

» Newer posts