I’m done with school now, degree and all, and still have a couple of weeks before I’m officially on the job. In the meantime I’ve been fooling around with some home automation hardware, specifically the veralite from micasaverde. While I haven’t spent too much time with the veralite yet my first impression is that it is still a little undercooked. Developer documentation is rough to non-existant, serial support is sketchy, and the Android app seems hit or miss. That said, I do like the box and there seems to be a ton of progress being made on the backend. In an effort to learn the Lua language used for plugin development, and to keep myself busy, I’ve taken on another hardware and software project. Pictured below is the first prototype of this project.
I’ve managed to get the nestest rom to run on my emulator. I’m still nowhere near complete but this is a good first step. Video is working, at least without sprites. Control input works, although there’s a bug floating around in there somewhere I’m currently working on getting the APU ( Audio Processing Unit) up and running. Below is a video of my emulator passing all standard opcode tests.
I’ve made significant progress since my first stumbling block. I’ve rewritten my 6502 core so that it is synthesizable and have successfully deployed it to my nanoboard. I have been able to tweak the data bus such that I can communicate with the internal cartridge, my PPU, and the external SRAM available on the nanoboard. This has been pretty tricky since it has been taking over 10 minutes to synthesize and my logic analyzer only has 16 Channels. I’ve found some methods to mitigate these issues and after uncovering a couple of fatal bugs in my PPU Core an image was finally rendered. The rendered screen isn’t what is expected but it is generating tiles from the cartridge data. If you look closely you’ll be able to see some blurry 8’s, 4’s commas and colons.
I’ve made significant progress on my 6502 FPGA Emulation, and even have a mostly complete layout of the NES Picture Processing Unit. I set up a test-bench that included RAM and cartridge simulation and logged the processor output to a text file that could be compared to the “golden” nestest log. I was able to debug all of the documented instructions and had begun to implement some of the undocumented instructions when I decided to try and load the processor into my FPGA. Unfortunately, this is where I learned that just because something can be simulated doesn’t mean it can be synthesized.
There’s an amazing project known as Visual 6502. They have created a transistor level net-list of the 6502 processor which can in turn be converted into synthesizable VHDL. As nice as this is, I’ve decided that would be far too easy and am going to go ahead and emulate the 6502 core before I fool around with a proper simulation. I’ve already poured through the available documents and laid out a framework for my emulation. The capture below is the first result from that process. That is the emulator executing the opcode 0x01 (Inderect X indexed OR with the accumulator) The A register isn’t actually visable but the processor is successfully loading the data from my simulated ROM and jumping to the correct memory locations based on the code I’ve provided. There is still a long way to go before the process is complete, but it is well on its way.