EngineeredEntropy

Author's details

Date registered: May 24, 2012

Latest posts

  1. PSoC 5LP Composite Video Decoder — September 15, 2017
  2. New Projects — September 15, 2017
  3. First Commercial Success — October 4, 2013
  4. Back To Work — September 29, 2013
  5. NES FPGA: Some Tricks Required — July 19, 2013

Most commented posts

  1. dllhost.exe High Processor Usage Fix — 3 comments
  2. FPGA NES: VGA (Part 3) — 1 comment

Author's posts listings

Jul 05

Arduino Garage Door Opener – Prototype

I’m done with school now, degree and all, and still have a couple of weeks before I’m officially on the job.  In the meantime I’ve been fooling around with some home automation hardware, specifically the veralite from micasaverde.  While I haven’t spent too much time with the veralite yet my first impression is that it …

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May 10

NES FPGA: First Run

I’ve managed to get the nestest rom to run on my emulator.  I’m still nowhere near complete but this is a good first step.  Video is working, at least without sprites.  Control input works, although there’s a bug floating around in there somewhere   I’m currently working on getting the APU ( Audio Processing Unit) up and …

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Apr 17

NES FPGA : Mini Breakthroughs

I’ve made significant progress since my first stumbling block.  I’ve rewritten my 6502 core so that it is synthesizable and have successfully deployed it to my nanoboard.  I have been able to tweak the data bus such that I can communicate with the internal cartridge, my PPU, and the external SRAM available on the nanoboard.  This has …

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Apr 05

Of Simulation and Synthesis

I’ve made significant progress on my 6502 FPGA Emulation, and even have a mostly complete layout of the NES Picture Processing Unit.  I set up a test-bench that included RAM and cartridge simulation and logged the processor output to a text file that could be compared to the “golden” nestest log.  I was able to debug all …

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Mar 22

FPGA 6502 Emulator: First Life

There’s an amazing project known as Visual 6502.  They have created a transistor level net-list of the 6502 processor which can in turn be converted into synthesizable VHDL.  As nice as this is, I’ve decided that would be far too easy and am going to go ahead and emulate the 6502 core before I fool around with a proper simulation.  I’ve …

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