NES FPGA : Mini Breakthroughs

I’ve made significant progress since my first stumbling block.  I’ve rewritten my 6502 core so that it is synthesizable and have successfully deployed it to my nanoboard.  I have been able to tweak the data bus such that I can communicate with the internal cartridge, my PPU, and the external SRAM available on the nanoboard.  This has been pretty tricky since it has been taking over 10 minutes to synthesize and my logic analyzer only has 16 Channels.  I’ve found some methods to mitigate these issues and after uncovering a couple of fatal bugs in my PPU Core an image was finally rendered.  The rendered screen isn’t what is expected but it is generating tiles from the cartridge data. If you look closely you’ll be able to see some blurry 8’s, 4’s commas and colons.

IMG_20130416_013526

 

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Of Simulation and Synthesis

I’ve made significant progress on my 6502 FPGA Emulation, and even have a mostly complete layout of the NES Picture Processing Unit.  I set up a test-bench that included RAM and cartridge simulation and logged the processor output to a text file that could be compared to the “golden” nestest log.  I was able to debug all of the documented instructions and had begun to implement some of the undocumented instructions when I decided to try and load the processor into my FPGA. Unfortunately, this is where I learned that just because something can be simulated doesn’t mean it can be synthesized.

Log Comparison

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