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Aug 14

FPGA NES: VGA (Part 3)

A video engineer, or really anybody who cares, would tell you that I’ve created a pretty inaccurate representation of the SMPTE color bar test pattern. As I’m not actually trying to calibrate any monitors I don’t fall into this category. I’ve modeled my test screen off of the Wikipedia description of SMPTE color bars. This project only generates a color simulation, ignoring the I and Q vectors, pluge pulse, and other underlying embedded signals. I’m satisfied with the results of this project and consider the original goal to be accomplished. Modifications to the code will most likely be required when it is integrated into the final NES project, but that is much farther down the road. The updated color generator code as well as a download link to the entire project are provided below.

[cc lang="vhdl"]
Library IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_Unsigned.all;

ENTITY VGAColor is
    Port(
        Clock,Reset : in STD_LOGIC;
        pixel : in STD_LOGIC_VECTOR(7 downto 0);
        pixelActive : in STD_LOGIC;
        row,column : in STD_LOGIC_VECTOR(0 to 9);
        animate : in STD_LOGIC;
        VSync, HSync : in STD_LOGIC;
        Red, Green, Blue : out STD_LOGIC_VECTOR(7 downto 0)
    );
end VGAColor;

Architecture structure of VGAColor is
    signal Red_sig,Green_sig,Blue_sig : STD_LOGIC_VECTOR(7 downto 0);
    signal animateCounter : STD_LOGIC_VECTOR (0 to 5);
    signal horizontalStart : STD_LOGIC_VECTOR (0 to 9);
    signal verticalStart : STD_LOGIC_VECTOR (0 to 9);
    signal horzAdd : integer := 1;
    signal vertAdd : integer := 1;
    constant pixelCount  : integer := 640;
    constant rowCount : integer := 480;

    constant firstRow : integer := 320;
    constant secondRow : integer := 40;
    constant columnWidth : integer := 91;
    constant secondWidth : integer := 105;
    constant firstBright : STD_LOGIC_VECTOR( 7 downto 0) := "10111111";

begin process(Clock, Reset)
    begin
        if (Reset = '1') then
            Blue_sig <= "00000000";
            Red_sig <= "00000000";
            Green_sig <= "00000000";
        elsif (Clock'event and Clock = '1' ) then
            if pixelActive = '1' then
                --2/3's color bars
                if row  < firstRow then
                    if column < (columnWidth*4) then
                        Green_sig= (columnWidth*4)) and (column(columnWidth*2)) and (column=(columnWidth*4)) and (column=(columnWidth*6)) then --and (column (columnWidth*2)) and (column= (columnWidth*4)) and (column(columnWidth*6)) and (column

Update:
Below is an updated VGAClock that includes Vblank, and Hblank, pulses.

VGAClock.vhd
[cc lang="vhdl"]
Library IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_Unsigned.all;

ENTITY VGAClock is
    Port(
        Clock, Enable, Reset: in STD_LOGIC;
        HSync, VSync, rowActive, columnActive, pixelActive : out STD_LOGIC;
        row,column : out STD_LOGIC_VECTOR(0 to 9);
        VBlank, HBlank : out STD_LOGIC
    );
end VGAClock;

Architecture structure of VGAClock is

    signal HSync_sig : STD_LOGIC := '1';
    signal VSync_sig : STD_LOGIC := '1';
    signal row_sig : STD_LOGIC_VECTOR(0 to 9) := "0000000000";
    signal column_sig : STD_LOGIC_VECTOR(0 to 9) := "0000000000";

    signal rowActive_sig : STD_LOGIC;
    signal columnActive_sig : STD_LOGIC;
    signal pixelActive_sig : STD_LOGIC;

    constant pixelCount  : integer := 640;
    constant HSyncTime   : integer := 95;
    constant HLeftBlank  : integer := 23;
    constant HRightBlank : integer := 47;

    constant VSyncTime   : integer := 2;
    constant VBlankLeft  : integer := 14;
    constant rowCount    : integer := 480;
    constant VBlankRight : integer := 32;

begin process(Clock, Reset)
    begin
        if (Reset = '1') then
            HSync_sig <= '1';
            VSync_sig <= '1';
            column_sig <= "0000000000";
            row_sig <= "0000000000";
            pixelActive_sig <= '0';
            rowActive_sig <= '1';
            columnActive_sig <= '0';
        elsif (Clock'event and Clock = '1') then
            --Done Pixels, enter HBlankLeft
            if(column_sig = (pixelCount-1)) then
                Hblank <= '1';
                rowActive_sig <= '0';
                column_sig

Sources:
SMPTE color bars
Related Posts:
FPGA NES: VGA (Part 1)
FPGA NES: VGA (Part 2)
Downloads:
SMPTE color bars (749)

1 comment

  1. Steve

    Very Cool. Nice project. I thought I would try out your SMPTE test pattern on my HDMI project. Your code is quite compact. I did hit a snag though – You dont have a “Blanking” signal from your timing generator. I tried to create one from the active pixel signal, and the active column and row signals but my HDMI formatter didnt like it.

    http://www.srkhdesigns.com/CBAVPB01.html

    I dont suppose you could add a blanking signal to your code? It would be nice to give my project a built in test pattern generator.

    thanks,

    regards,
    Steve

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