PSoC 5LP Composite Video Decoder

As I mentioned previously I’ve been doing some work with the PSoC Family of microcontrollers from Cypress.  One of my more recent projects has been a Composite video decoder prototype.  All processing for this project is done inside of the PSoC with the only external component being a terminating resistor.  Really all of the processing is being done in the UDB/Peripheral portion of the PSoC with DMA being used to handle data transfer from the video source to the LCD.

I haven’t verified the timing but I believe I’m displaying the video at 320×240 @ ~60FPS.    It’s a single bit black or white signal at the moment.  I may be able to get that up to a four level grayscale image.  There are some clock timing issues which are causing problems with getting the video signal synchronized with 0,0 on the LCD.  Now that I’ve got a proof of concept working I’ll likely start the next revision from scratch to try and avoid those issues.  Once that’s done I should be able to share the source along with some more technical posts.

A quick demonstration video is provided below:

 

New Projects

It’s been a little while.  A lack of time and interesting projects combined to keep me from posting.  I bought a 3D printer some time ago but that’s mainly been a story about an EE learning how to use 3D modeling software.  I’ve become pretty proficient with it though and may try to include it in some future designs/projects.  

I came across the PSoC family of microcontorollers a few years ago as well and they’ve subsequently become my favorite thing in the world.  I’ve used them extensively in my professional and personal projects, nothing I’ve ever really been able to post about but I’ve got a few active projects that I should be able to share in the near future.  

First Commercial Success

After ordering the wrong buffer chip for my Logic Cube I started poking around and managed to get a commercial rom to run.  It seems my issues are a result of timing problems with my new memory mapping module.  The attempt shown below locked up at the title screen but I have since managed to start the demo video that follows.  Unfortunately since I haven’t implemented sprites its less of a video and more of a static background.  Assuming the chip that came in today is the correct version I hope to be running on 32 channels and make more progress this weekend.

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Back To Work

It’s been a little while since I’ve posted any progress on any of my projects.  I’ve been recently employed as a full time design engineer and have finally transitioned back into a schedule that allows me to work on some of my own interests again.  I’ve started up working on my NES emulator and had my first success loading a cartridge from an SD Card.  I’m stuck again as the emulator locks up when after it’s partially rendered the screen. Debugging has gotten more difficult as time goes on as it now takes 15-20 minutes to compile the design and only having 16 channels on my logic analyzer means recompiling more frequently to figure out what’s gone wrong.  I have parts on order to perform an upgrade to 32 channels but until then I expect progress will be a bit slow.  I’m hoping to have the parts installed and be able to read the entire address and data buses along with any status bits I need by the end of the week.

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NES FPGA: Some Tricks Required

I’ve run into a bit of a road block with my NES Emulation.  I’ve been trying to keep as much of the project as possible in standard VHDL without relying on pre-built libraries or modules.  In order to make testing, as well as end-result use, easier I’d like to be able to load files off of an SD Card using the FAT file system.  Unfortunately attempting to do this in VHDL seems far from straightforward and is certainly more involved than I’m looking to get for this project.  As such I’ve resorted to a wishbone based TSK3000 processor module and some C code to perform FAT related functions, parsing of the INES header, and all cartridge I/O functions.

 

At this point I’ve been moderately successful with this implementation.  Mounting the FAT file system works.  I can read the available files and load the desired file.  I can even get the nestest rom to run after loading it from the SD Card.  There is a catch though,  and it is pretty big.  In order for the loaded file to run I have to slow the NES’s clock down about 50x.  It’s not going to be possible to get  any meaningful gain out of the processor and I don’t want to rearrange the entire project to make use of the shared memory bus.  I’ve used up both SDRAM Chips (one for the CPU and one for the PPU) so I’m going to have to do some consolidation.

 

There is more than enough memory available in a single SDRAM chip for the entire project.  The problem is that I need to be able to access each memory location simultaneously (CPU RAM, PPU RAM, Cartridge) and the chips are single port.  I intend on solving this with another VHDL module.  Using the 50MHz clock should allow me to fake a triple port or more memory chip by sequentially reading out the requested memory addresses and latching them to independent outputs.